1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a semiconductor device having first and second signal lines and a MOS transistor for coupling the lines.
2. Description of the Background Art
System LSIs have been developed which are mounted with DRAM core cells and logic circuits. In order to improve a data transfer rate, input and output of hundreds of bits of data at a time is enabled between a DRAM core cell and a logic circuit. In addition, an input terminal for a one-bit write mask signal is provided for every plurality of bits, and controlling of the write mask signal enables rewriting of data of memory cells of the corresponding plurality of bits to be inhibited.
FIG. 12 is a block diagram showing an entire structure of such a DRAM core cell 30. In FIG. 12, the DRAM core cell 30 includes a row/column address buffer+clock generation circuit 31, a row/column decoder circuit 32, a memory mat 33 and a data input/output circuit 34. In the DRAM core cell 30, 8 k bits of data DQ1-8 k (k: integer not less than 1) can be input and output at a time and an input terminal for a one-bit write mask signal WM is provided for every 8 bits of data.
The row/column address buffer+clock generation circuit 31 generates row address signals RA0-m, column address signals CA0-CAm, a read clock signal CLKR and a write clock signal CLKW in accordance with external address signals A0-Am (m: integer not less than 0) and external control signals /RAS, /CAS, /WE to control the entire DRAM core cell 30.
The memory mat 33 includes a plurality of sense amplifier bands SA1-SA3 and memory cell arrays MA1 and MA2 arranged between the bands. The memory cell arrays MA1 and MA2 each include a plurality of memory cells for storing one bit of data. The plurality of memory cells are grouped by a predetermined number, 8 k bits. Each memory group is arranged at a predetermined address deter-mined by a row address and a column address.
The row/column decoder circuit 32 designates addresses of the memory cell arrays MA1 and MA2 in accordance with the row address signals RA0-RAm and the column address signals CA0-CAm applied from the row/column address buffer+clock generation circuit 31. In the sense amplifier bands SA1 and SA2, a sense amplifier+input/output control circuit group which will be described later is provided. The sense amplifier+input/output control circuit group connects the number 8 k of memory cells at the addresses designated by the row/column decoder circuit 32 to the data input/output circuit 34. The data input/output circuit 34 includes a write driver+read amplifier band 35 and an input/output buffer group 36. In the write driver+read amplifier band 35, a write driver group and a read amplifier group are provided.
The read amplifier group operates in synchronization with the read clock signal CLKR to apply read data Q1-Q8k from the number 8 k of selected memory cells to the input/output buffer group 36. The input/output buffer group 36 externally outputs the read data Q1-Q8k from the read amplifier group in response to an external control signal /OE. The write driver group operates in synchronization with the write clock signal CLKW to write external write data D1-D8k into the number 8 k of selected memory cells. Of the number 8 k of memory cells, no data will be written into the memory cells designated by write mask signals WM1-WMk.
Each of the memory cell arrays MA1 and MA2 includes the number 8 k of memory blocks MB provided corresponding to the data DQ1-DQ8k. Each memory block MB, as shown in FIG. 13, includes a plurality of memory cells MC arranged in a plurality of rows and columns, a plurality of word lines WL provided corresponding to the plurality of rows, and a plurality of bit line pairs BL, /BL provided corresponding to the plurality of columns. The memory cell MC is a known MC including an N channel MOS transistor Q for access and a capacitor C for information storage.
When a word line WL corresponding to the row address signal RA0-RAm is brought to a logical high or a xe2x80x9cHxe2x80x9d level as a selection level by the row/column decoder circuit 32, an N channel MOS transistor Q of a memory cell MC at a row corresponding to the word line WL is rendered conductive to enable data writing/reading of the memory cell MC. In writing operation, after activating a memory cell MC by forcing one word line WL to a xe2x80x9cHxe2x80x9d level as the selection level, one bit line of a bit line pair BL, /BL is forced to a xe2x80x9cHxe2x80x9d level and the other to a logical low or a xe2x80x9cLxe2x80x9d level in accordance with the write data D. As a result, a potential of the bit line is written into a capacitor C of a desired memory cell MC. In reading operation, after equalizing potentials of the bit line pair BL, /BL to VBL (=VCC/2), the memory cell MC is activated by forcing one word line WL to a xe2x80x9cHxe2x80x9d level as the selection level. As a result, a minute potential difference is generated between BL and /BL of each bit line pair according to storage data of the memory cell MC. By amplifying a minute potential difference between bit lines of each pair to a power supply voltage Vdds and then detecting a potential difference between bit lines of one bit line pair, data in a desired memory cell MC can be read. The number 8 k of memory blocks MB are arrayed in a direction in which the word lines extend and the word lines WL are shared by the number 8 k of memory blocks MB.
FIG. 14 is a circuit block diagram showing a structure of a part related to writing/reading of the data DQ1. In FIG. 14, provided are a write driver 37 and a write data line pair GIOW, /GIOW for the writing of the data D1, and a read amplifier 38 and a read data line pair GIOR, /GIOR for the reading of the data Q1.
The write driver 37 is arranged in the write driver+read amplifier band 35 shown in FIG. 12 for forcing one of the write data lines GIOW and /GIOW to a xe2x80x9cHxe2x80x9d level and the other to a xe2x80x9cLxe2x80x9d level in accordance with the write data D1 in writing operation. The read amplifier 38 is arranged in the write driver+read amplifier band 35 for detecting a potential difference between a read data line pair GIOR, /GIOR to generate the read data Q1 and externally output the same through the output buffer in reading operation.
The write data line pair GIOW, /GIOW is arranged to cross the memory arrays MA1 and MA2 and the sense amplifier bands SA1-SA3 shown in FIG. 12 and has its one end connected to the write driver 37. The read data line pair GIOR, /GIOR is arranged to cross the memory arrays MA1 and MA2 and the sense amplifier bands SA1-SA3 and has its one end connected to the read amplifier 38.
A sense amplifier+input/output control circuit 40 is provided commonly for one pair of bit lines BL1 and /BL1 included in a memory block MB of the memory cell array MA1 and one pair of bit lines BL2 and /BL2 included in a memory block MB of the memory cell array MA2. The sense amplifier+input/output control circuit 40 is provided, for example, for each odd-numbered bit line pair BL, /BL of the memory cell arrays MA1 and MA2 and arranged at the sense amplifier band SA2. Sense amplifier+input/output control circuits each for each even-numbered bit line pair BL, /BL of the memory cell arrays MA1 and MA2 are arranged in the sense amplifier bands SA1 and SA3, respectively.
The sense amplifier+input/output control circuit 40 includes N channel MOS transistors 41 to 44, equalizers 45 and 46, a sense amplifier 47, a write gate 50 and a read gate 60. The N channel MOS transistors 41 and 42 are connected between the bit lines BL1 and /BL1 of the memory cell array MA1 and nodes N1 and N2, respectively, and each have a gate receiving a signal SHR1. The N channel MOS transistors 43 and 44 are connected between the bit lines BL2 and /BL2 of the memory cell array MA2 and the nodes N1 and N2, respectively, and each have a gate receiving a signal SHR2. When the signal SHR1 attains a xe2x80x9cHxe2x80x9d level as an activation level, the N channel MOS transistors 41 and 42 become conductive to cause the sense amplifier+input/output control circuit 40 to be coupled with the bit line pair BL1, /BL1 of the memory cell array MA1. When the signal SHR2 attains a xe2x80x9cHxe2x80x9d level as the activation level, the N channel MOS transistors 43 and 44 become conductive to cause the sense amplifier+input/output control circuit 40 to be coupled with the bit line pair BL2, /BL2 of the memory cell array MA2.
The equalizer 45 is activated to equalize potentials of the bit line pair BL1, /BL1 of the memory cell array MA1 to the bit line potential VBL (=Vdds/2) when a signal BLEQ1 is at a xe2x80x9cHxe2x80x9d level as the activation level. The equalizer 46 is activated to equalize potentials of the bit line pair BL2, /BL2 of the memory cell array MA2 to the bit line potential VBL when a signal BLEQ is at a xe2x80x9cHxe2x80x9d level as the activation level. The sense amplifier 47 is activated in response to signals SE and /SE attaining a xe2x80x9cHxe2x80x9d level and a xe2x80x9cLxe2x80x9d level as the activation level, respectively, to amplify a potential difference between the bit line pair BL1, /BL1 or BL2, /BL2 connected to the nodes N1 and N2 by the N channel MOS transistors 41 and 42 or 43 and 44 to the power supply voltage Vdds.
The write gate 50 includes N channel MOS transistors 51-54. The N channel MOS transistors 51 and 52 are connected in series between the write data line GIOW and the node N1 and have gates which receive the signals WM1 and CSLW, respectively. The N channel MOS transistors 53 and 54 are connected in series between the write data line /GIOW and the node N2 and have gates which receive the signals WM1 and CSLW, respectively.
When the column selecting signal CSLW attains a xe2x80x9cHxe2x80x9d level as the selection level, the N channel MOS transistors 52 and 54 become conductive. When the write mask signal WM1 is at a xe2x80x9cLxe2x80x9d level, the N channel MOS transistors 51 and 53 become non-conductive to inhibit writing of the data D1. When the write mask signal WM1 is at a xe2x80x9cHxe2x80x9d level, the N channel MOS transistors 51 and 53 become conductive to allow writing of the data D1.
The read gate 60 includes N channel MOS transistors 61-64. The N channel MOS transistors 61 and 62 are connected in series between a line of a ground potential GND and the read data line /GIOR, while the N channel MOS transistors 63 and 64 are connected in series between the line of the ground potential GND and the read data line GIOR. The N channel MOS transistors 61 and 63 have gates connected to the nodes N1 and N2, respectively, and the N channel MOS transistors 62 and 64 have gates both of which receive a signal CLSR.
When the column selecting signal CSLR attains a xe2x80x9cHxe2x80x9d level as the selection level, the N channel MOS transistors 62 and 64 become conductive. When the nodes N1 and N2 are at a xe2x80x9cHxe2x80x9d level and a xe2x80x9cLxe2x80x9d level, respectively, the N channel MOS transistor 61 becomes conductive and the N channel MOS transistor 63 becomes non-conductive, so that of the read data lines GIOR and /GIOR precharged to a xe2x80x9cHxe2x80x9d level, the read data line /GIOR is grounded. When the nodes N1 and N2 are at a xe2x80x9cLxe2x80x9d level and a xe2x80x9cHxe2x80x9d level, respectively, the N channel MOS transistor 63 becomes conductive and the N channel MOS transistor 61 becomes non-conductive, so that of the read data lines GIOR and /GIOR precharged to a xe2x80x9cHxe2x80x9d level, the read data line GIOR is ground.
Next, operation of a part related to writing/reading of the data DQ1 shown in FIG. 14 will be described. Description will be here made of a case where a bit line pair BL1, /BL1 of the memory cell array MA1 is selected. It is assumed that the write mask signal WM1 is at a xe2x80x9cHxe2x80x9d level.
In writing operation, first the signal SHR2 attains a xe2x80x9cLxe2x80x9d level as an inactivation level, so that the N channel MOS transistors 43 and 44 become non-conductive to cause the nodes N1 and N2 to be cut off from the memory cell array MA2. In addition, the bit line equalizing signal BLEQ1 attains a xe2x80x9cLxe2x80x9d level as the inactivation level to inactivate the equalizer 45, so that equalization of the bit line pair BL1, /BL1 of the memory cell array MA1 is stopped.
Next, a column selecting signal CSLW corresponding to the column address signal CA1-CAm is brought to a xe2x80x9cHxe2x80x9d level as the selection level, so that the write gate 50 corresponding to the column selecting signal CSLW becomes conductive to cause the write data line pair GIOW, /GIOW to be coupled with the bit line pair BL1, /BL1 through the write gates 50, the nodes N1 and N2 and the N channel MOS transistors 41 and 42. In addition, the write driver 37 brings one of the write data lines GIOW and /GIOW to a xe2x80x9cHxe2x80x9d level and the other to a xe2x80x9cLxe2x80x9d level in accordance with the write data D1.
Next, the sense amplifier activation signals SE and /SE are forced to a xe2x80x9cHxe2x80x9d level and a xe2x80x9cLxe2x80x9d level as the activation level, respectively, to activate the sense amplifier 47, so that a potential difference between the bit line pair BL1, /BL1 is amplified to the power supply voltage Vdds by the sense amplifier 47. Also, a word line WL corresponding to the row address signal RA0-RAm is brought to a xe2x80x9cHxe2x80x9d level as the selection level to activate a memory cell MC corresponding to the word line WL, so that the potential of the bit line BL1 or /BL1 is written into the memory cell MC.
In reading operation, first the signal SHR2 attains a xe2x80x9cLxe2x80x9d level as the inactivation level to render the N channel MOS transistors 43 and 44 non-conductive, so that the nodes N1 and N2 are cut off from the memory cell array MA2. In addition, the bit line equalizing signal BLEQ1 attains axe2x80x9cLxe2x80x9d level as the inactivation level to inactivate the equalizer 45, so that equalization of the bit line pair BL1, /BL1 of the memory cell array MA1 is stopped.
Next, a word line WL corresponding to the row address signal RA0-RAm is brought to a xe2x80x9cHxe2x80x9d level as the selection level to activate a memory cell MC corresponding to the word line WL, so that a minute potential difference is generated between the bit line pair BL1, /BL1 in accordance with the storage data of the memory cell MC.
Next, the sense amplifier activation signals SE and /SE are brought to a xe2x80x9cHxe2x80x9d level and a xe2x80x9cLxe2x80x9d level as the activation level to activate the sense amplifier 47, so that a potential difference between the bit lines BL1 and /BL1 is amplified to the power supply voltage Vdds. More specifically, of the bit lines BL1 and /BL1, a bit line whose potential is higher than the precharge potential Vdds/2 is set at the power supply potential Vdds and the remaining bit line is set at the ground potential GND. As a result, either the N channel MOS transistor 61 or 63 of the read gate 60 becomes conductive and the other becomes non-conductive.
Subsequently, a column selecting signal CSLR corresponding to the column address signal CA0-CAm is brought to a xe2x80x9cHxe2x80x9d level as the selection level to render the N channel MOS transistors 62 and 64 of the read gate 60 corresponding to the column selecting signal CSLR conductive, so that one of the read data lines GIOR and /GIOR precharged in advance to a xe2x80x9cHxe2x80x9d level is grounded through the N channel MOS transistors 62 and 61, or 64 and 63 to attain a xe2x80x9cLxe2x80x9d level. The read amplifier 38 detects a potential difference between the read data line pair GIOR, /GIOR to generate the data Q1 of a logic corresponding to the detection result and externally output the same through the output buffer.
Conventionally, since amplitude voltages of the bit lines BL and /BL, amplitude voltages of the data lines GIOW, /GIOW, GIOR and /GIOR and amplitude voltages of the column selecting signals CSLW and CSLR are the same, MOS transistors having the same breakdown voltage, that is, having a gate oxide film of the same thickness are used for the write gate 50, the read gate 60 and the sense amplifier 47.
In recent years, however, as a peripheral power supply of the DRAM core cell 30 is designed to have a lower voltage and the number of the data lines GIOW, /GIOW, GIOR and/GIOR and the column selecting signals CSLW and CSLR is increased, it is necessary to set these amplitude voltages to be the same as a peripheral power supply voltage, thereby reducing consumption of electricity.
Simply decreasing amplitude voltages of the column selecting signals CSLW and CSLR, however, leads to reduction in a source-drain current Id flowing through the N channel MOS transistors 52, 54, 62 and 64 to slow down writing/reading operation.
Another possible method is amplifying an amplitude of column selecting signals CSLW and CSLR whose amplitude voltage is low by a level converting circuit, which requires time for level conversion to slow down writing/reading operation.
On the other hand, since it is necessary to write as high a voltage as possible into a capacitor C of a memory cell MC to make a data holding time longer, it is undesirable to reduce a power supply voltage Vdds for the sense amplifier 47. Accordingly, uniformly thinning a gate oxide film of a MOS transistor for increasing a source-drain current Id results in breakdown of the MOS transistor by the power supply voltage Vdds for the sense amplifier 47.
An object of the present invention is to provide a semiconductor device having low current consumption and a high operating rate.
A semiconductor device according to the present invention includes a first signal line supplied with a signal having one level at a first potential and the other level at a reference potential, a second signal line precharged to a second potential predetermined, a first MOS transistor having an input electrode connected to the first signal line and responsive to a potential of the first signal line exceeding its threshold potential to become conductive, and a second MOS transistor responsive to application of a control signal which allows transmission of a signal on the first signal line to the second signal line to become conductive to connect the first MOS transistor between the second signal line and a line of the reference potential, with a gate oxide film of the second MOS transistor formed to be thinner than that of the first MOS transistor. Since the gate oxide film of the second MOS transistor is made thin, an amplitude voltage of the control signal can be lowered to reduce electricity consumption. In addition, since no level converting circuit for amplifying the control signal whose voltage is reduced is necessary, operating rate will not be lowered. Also, reduction in the size of the second transistor is possible to realize reduction in a chip area.
Preferably, the semiconductor device according to the present invention further includes a third signal line supplied with a complementary signal of the signal applied to the first signal line, a fourth signal line to be precharged to the second potential, a third MOS transistor having an input electrode connected to the third signal line and responsive to a potential of the third signal line exceeding its threshold potential to become conductive, and a fourth MOS transistor responsive to application of the control signal to become conductive to connect the third MOS transistor between the fourth signal line and the line of the reference potential, with a gate oxide film of the fourth MOS transistor formed to be thinner than that of the third MOS transistor. In this case, the signals and their complementary signals can be transmitted.
Also preferably, the semiconductor device of the present invention includes the first and the second MOS transistors connected in series between the second signal line and the line of the reference potential, the third signal line supplying a complementary signal of the signal applied to the first signal line, the fourth signal line precharged to the second potential, and a third MOS transistor having a first electrode connected to the fourth signal line, a second electrode connected to a node between the first and the second MOS transistors and an input electrode connected to the third signal line, and responsive to a potential of the third signal line exceeding its threshold potential to become conductive, with a gate oxide film of the second MOS transistor formed to be thinner than that of the third MOS transistor. In this case, the signals and their complementary signals can be transmitted. In addition, because the second MOS transistor is shared by the first and the third MOS transistors, a less number of transistors are required.
Another semiconductor device according to the present invention includes a first signal line supplied with a signal having one level at a first potential and the other level at a reference potential, a second signal line precharged to a second potential predetermined, a sense amplifier for amplifying a potential difference between a potential of the second signal line and the second potential and applying a signal having one level at a third potential higher than the first potential and the other level at the reference potential to the second signal line, a first MOS transistor having a first electrode connected to the first signal line and responsive to application of a first control signal allowing a signal on the first signal line to be transmitted onto the second signal line to become conductive, and a second MOS transistor connected between a second electrode of the first MOS transistor and the second signal line and responsive to application of a second control signal inhibiting a signal on the first signal line to be transmitted onto the second signal line to become non-conductive, with a gate oxide film of the first MOS transistor formed to be thinner than that of the second MOS transistor. Since the gate oxide film of the first MOS transistor is made thin, an amplitude voltage of the first control signal can be lowered to reduce electricity consumption. In addition, since no level converting circuit for amplifying the first control signal whose voltage is reduced is necessary, operating rate will not be lowered. Also, reduction in the size of the first transistor is possible to realize reduction in a chip area.
A further semiconductor device according to the present invention includes a first signal line supplied with a signal having one level at a first potential and the other level at a reference potential, a second signal line precharged to a second potential predetermined, a sense amplifier for amplifying a potential difference between a potential of the second signal line and the second potential and applying a signal having one level at a third potential higher than the first potential and the other level at the reference potential to the second signal line, a first MOS transistor having a first electrode connected to the first signal line and responsive to application of a control signal allowing a signal on the first signal line to be transmitted onto the second signal line to become conductive, and a second MOS transistor connected between a second electrode of the first MOS transistor and the second signal line and receiving the third potential at its input electrode and being kept conductive, with a gate oxide film of the first MOS transistor formed to be thinner than that of the second MOS transistor. Since the gate oxide film of the first MOS transistor is made thin, an amplitude voltage of the control signal can be lowered to reduce electricity consumption. In addition, even when a potential of the second signal line is set at the third potential by the sense amplifier, dielectric breakdown of the first MOS transistor can be prevented because a potential lower than the third potential by a threshold voltage of the second MOS transistor is applied to the first MOS transistor.
Also preferably, each MOS transistor includes a gate oxide film and an active region formed on a surface of a semiconductor substrate and an active region of a MOS transistor having a relatively thick gate oxide film and an active region of a MOS transistor having a relatively thin gate oxide film are formed separately from each other. In this case, improvement of reliability and reduction of a layout area can be realized.